This invention relates to semiconductor memory devices, and more particularly to a system for partitioning a high-density N-channel MOS memory device of the type employing an array of one-transistor memory cells.
MOS random access memory (RAM) devices are widely used in the manufacture of digital equipment, particularly minicomputers. The capabilities and cost advantages of these devices have increased steadily over the past few years. The cost per bit of storage using MOS RAMs goes down as the number of bits or memory cells per package goes up. At various times, successively larger RAM's have become standards in the industry, such as 256 bit, 512 bit, 1024 bit, and now 4096 bit. A RAM containing 4096 bits, for exaple is shown in U.S. Pat. No. 3,940,747 issued Feb. 24, 1976 to Kuo and Kitagawa, assigned to Texas Instruments. At the present time, manufacturers of semiconductor devices are attempting to produce 16,384 bit or "16K" RAM's; see Electronics, Feb. 19, 1976, pp. 116-121.
As the number of bits in a semiconductor chip is increased, the cell size decreases, and the magnitude of the storage capacitor in each cell of necessity decreases. Also, the number of cells on a digit line in the array of cells increases, so the capacitance of this line increases. These factors reduced the magnitude of the data signal which exists on a digit line. A full logic level, i.e., the difference between a "1" and a "0", in one of these devices may be perhaps 10 or 12 volts; however, the difference in voltage between a "1" and a "0" for the data coupled to a digit line in the memory array from the selected one-transistor cell may be only one or two tenths of a volt. In a high density memory design, a sense amplifier circuit to detect these low-level signals is a critical element. Examples of sense amplifiers are shown in U.S. Pat. No. 3,940,747 mentioned above, and in U.S. Pat. No. 3,838,404 to Heeren, as well as in Electronics, Sept. 13, 1973, Vol. 46, No. 19, pp. 116-121, and IEEE Journal of Solid State Circuits, October, 1972, p. 336, by Stein et al.
In memory devices requiring high packing density, such as in the 16K RAM, the power dissipation becomes a critical factor, and the systems previously proposed have shortcomings in this regard.
It is the principal object of this invention to provide an improved system for partitioning the memory cell array and sense amplifier arrangement for an MOS RAM, and in particular system which is of low power dissipation.
The smallest proven sense amplifier circuits, even though advantageous to save space on the chip since so many are needed, are not acceptable due to high power dissipation. Although power reduction can be achieved by selectively turning off the load transistors in the flip-flop circuit of a typical sense amplifier, this method imposes restrictions which are disadvantageous. Read/modify/write and paging mode operations will be inhibited unless the center decode approach is used, at the cost of large chip size and reduced sensitivity. Also, the refreshing operation will be very poor due to the lack of a current supply in the addressed column.
Another recently developed sense amplifier has low power dissipation; however, it has the drawbacks of high instantaneous current, relatively poor sensitivity, and complex clock timing, and further requires a costly center decode layout to achieve paging mode and read/modify/write operation.